1. Field of the Invention
The present invention relates to an integrated circuit layout method, and more particularly to a method for implementing the layout of an integrated circuit containing an operational amplifier.
2. Description of the Prior Art
Operational amplifiers are among the most widely used electronic devices today, being used in a vast number of consumer, industrial, and scientific devices. An operational amplifier (hereinafter OP) is a DC-coupled high-gain electronic voltage amplifier with differential input terminals and, usually, a single output terminal. In its ordinary usage as a unit-gain buffer, the output of the OP is controlled by negative feedback which, because of the amplifier's high gain, almost completely determines the output voltage for any given input.
FIG. 1A shows a plan view illustrating a source driver layout 2. As shown in FIG. 1A, the source driver 10 includes two areas: core area 12 and pad area 14. The core area 12 is the area where some digital/analog circuits located for pixel driving. There are pads 16 disposed on the pad area 14 and used to electrically connect inputs/outputs of the digital/analog circuits in the core area 12 to external circuits.
FIG. 1B shows a plan view illustrating the core area 12 of the source driver in FIG. 1A. As shown in FIG. 1B, there are plural channels 18 and output buffets disposed in the core area 12. Each output buffer is exemplified by OP 20. Each of the channels 18 is electrically connected to the non-inverting input terminal of the OP 20. The inverting input terminal of the OP 20 is connected to the output of the OP 20.
FIG. 1C shows a schematic diagram illustrating a conventional layout pattern 10 of a part of the source driver. The layout pattern 10 includes an OP main body 20, an output pad 16 and an output path 111. The OP main body 20 includes the inverting input terminal 101, the non-inverting input terminal (not shown) and an output terminal 102 connected to the output pad 16 via the output path 111. The output terminal 102 connects to the inverting input terminal 101 via the feedback path 112. Although not explicitly specified in the figure, the OP main body 20 may further contain other elements such as elements for input stage as well as elements for output stage. The OP main body 20, the inverting input terminal 101 and the output terminal 102 are disposed within the core area 12, while the output pad 16 is disposed in the pad area 14. The output path 111 is disposed in the core area 12 and the pad area 14 both, while the feedback path 112 is disposed inside the OP 20.
FIG. 1D shows the equivalent circuit 10E corresponding to the layout pattern 10 in FIG. 1C. The circuit 10E includes an OP 100E, a first resistor R111, a second resistor R112 and the output pad N103. The OP 100E, the inverting input node 101E, the output node N102, the output pad N103, the first resistor R111 and the second resistor R112 in the equivalent circuit 10E are respectively equivalent to the OP main body 20, the inverting input terminal 101, the output terminal 102, the output pad 103, the output path 111 and the feedback path 112 in the layout pattern 10. As shown in FIG. 1D, the input voltage Gin, the feedback voltage Gfd and the output voltage Gout are the voltage respectively disposed at the non-inverting input node 101P, the output node N102 and the output pad N103. Referring to both FIG. 1C and FIG. 1D, it can be noted from the equivalent circuit 10E that the feedback path 112 forms a feedback path for the OP to operate in a feedback mode. As shown in FIG. 1D, the input voltage (Gin) in OP 100E is equal to the voltage (Gfd) in the output node N102. However, the voltage (Gfd) in the output node N102 is not equal to the voltage (Gout) in the output path because of the existence of the first resistor R111. Therefore, the output voltage (Gout) of the OP 100E is not equal to the input voltage (Gin) of the OP 100E. Because the input voltage is not equal to the output voltage in OP 100E, it would affect the display result of the display panel.
An OP typically functions as a voltage follower to drive, i.e., to provide a sufficient current and a steady voltage for, the next stage circuit. Practically, however, any routing path formed in an integrated circuit layout, such as the output path 111 or the feedback path 112 shown in FIG. 1C, possesses more or less resistance. Such resistance generally renders a voltage drop across the routing path and thus results in an output voltage offset or deviation. To a certain extent, the conventional routing scheme shown in FIG. 1C suffers from such output voltage offset problem, since the output path 111 usually runs a long way between the output terminal 102 lying in the OP main body 20 and the output pad 103 such that the resistance thereof is not small enough to be neglected. If the OP 20 in FIG. 1B is designed to provide a current I for the next stage circuit, for example, then a voltage drop V=I*R will arise when the resistance of the first resistor R111 (corresponding to the output path 111) is R. Therefore, the different lengths of the plural output paths 111 of the plural OPs 20 result in different output characteristics at the output pads 16.
A way for resolving the foregoing problem is therefore desired.